This invention relates to frequency synthesisers of the phase lock loop type. Such synthesisers include a voltage controlled variable frequency oscillator (VFO), a high stability clock pulse generator serving as a frequency reference, dividing means for reducing the frequency of the signal produced by the VFO, and a phase comparator which compares the relative phases of the signals produced by the dividing means and generator, the output of the phase comparator being applied as a frequency control signal via a loop filter to the VFO.
The invention more particularly relates to such synthesisers in which the dividing means at least includes a successive addition rate multiplier of the type which, for each input pulse, adds a predetermined increment Y to any accumulated value stored in an accumulator therein and gives an overflow pulse each time the capacity C (where C.gtoreq.Y) of the accumulator is reached or exceeded, whilst leaving any excess as a residue in the accumulator.
Successive addition rate multipliers, sometimes referred to as adjustable accumulators because the increment Y is usually adjustable in order to change the frequency division ratio, have the particular advantage that--as explained in United Kingdom Patent Specification No. 1,447,418--the residue in the accumulator at any time is a direct function of the time interval between the instant of occurrence of the immediately-preceding overflow pulse and the instant at which that pulse would have occurred if all the pulses were evenly spaced in time (i.e. with no phase jitter). The patent specification shows how this residue can be used to provide a correction signal which, when added to the output signal of the phase comparator in the appropriate sense and magnitude, compensates for any variation in the latter caused by the jitter in the pulse rate of the overflow pulses. Thus any wandering of the VFO frequency due to the jitter is considerably reduced by the correction signal which, in effect, predicts the phase jitter and compensates therefor.
Tests on the said known synthesiser showed that, in order for the effect of the jitter caused by the subtraction of pulses by the rate multiplier to be inaudible on a pure tone, the cancellation of the sidebands by the correction signal had to reduce them from a level greater than the carrier to about -30 dB with respect to the carrier. This requires an accuracy of about 3% in the nulling of the jitter and this is difficult where a wide frequency range, for example 20:1, is required. This gives rise to the problems that not only are close tolerance components required but also a difficult `setting up` procedure is involved. A further difficulty is that temperature drift in some of the components also affect the accuracy and might even make the 3% impossible to achieve in some circumstances.